Job Description:

This position will be critical to shaping the next generation of FPGA products from Xilinx, the leader in FPGAs.  The successful candidate for this position will join a technology leader, a rapidly growing organization and be an integral member of a skilled and motivated team.  The job will involve architecting a cutting edge synthesis, place and route methodology for implementing challenging designs. The successful candidate will have to define the complete RTL to GDSII flow including chip finishing steps in advanced process nodes.

Requirements:

• 10+ years experience developing flows for synthesis, place and route with Synopsys or Cadence tools.
• Strong experience with DSM ASIC methodologies including advanced DFM, DFT, OCV, signoff methodologies
• Should have successfully taped out DSM ASIC chips and have deep understanding of all aspects of ASIC design and implementation, including package, test and foundry interfaces
• Proven experience with high-speed interface/DDR integration
• Should be motivated, self-starter.
• Should be proficient in Tcl/Perl
• Excellent communication skills
• BTech/BE/BSEE with 10+ years of experience. MTech/ME/MSEE preferred.